Custom EMIPAK 1B Package With Flexible Pinout Options
Challenge
An onboard charger (OBC) customer developed a design with a custom power module from a competitor but was dissatisfied with the electrical and thermal performance of the LLC resonant converter’s output stage. Simulation results showed very high peak junction temperatures for some of the silicon die during operation.
Although the system had built-in mechanical features to improve thermal dissipation, these were not fully functional across the full dimensional area of the module. In particular, a cooling channel with coolant liquid only efficiently covered a small portion of the whole power module area.
Due to the late stage in the overall design, duplicating the existing pinout was a key requirement to avoid costly and time-consuming redesign costs for the custom aluminum heatsink and chassis of the OBC.
The overall objective was to reduce peak junction temperature without compromising the mechanical design and make the design function more efficiently.
Solution
Vishay’s EMIPAK 1B package option utilizes a pin matrix structure with the potential for 89 PressFit pin locations. These are available in a grid format with a fixed pitch of 3.2 mm in the x and y dimensions.
In the original design, the concentration of the die locations resulted in some specific hotspots where some of the die thermally affected each other inside the module. Integrating the latest Vishay FRED Pt® GEN 5 silicon technology provided superior electrical and thermal performance during operation. This ultrafast technology is optimized for LLC output stage applications and provides lower power losses, and therefore less heat to dissipate.
The integrated cooling channel was positioned in a fixed mechanical location. Due to the EMIPAK 1B pinout options, it was possible to spread out the silicon die over a larger area of the direct bond copper (DBC). This improved efficiency by removing, reducing, and specifically locating areas of heat concentration inside the module relative to the cooling channel location.
Benefit
The mechanical flexibility of the EMIPAK 1B due to its customizable PressFit pins and internal layout enables the optimization of silicon die locations inside the module to maximize electrical and thermal performance. Utilizing the latest Vishay FRED Pt® GEN 5 Silicon technology ensures excellent thermal performance and reduced junction temperatures during operation.
Combining these technologies enabled our customer to avoid a costly redesign or the need to use larger and much more expensive silicon die in their OBC.
Additional Case Studies
Avoiding a Complete Redesign After a Panel Potentiometer was Made Obsolete
Challenge
The customer approached Vishay when their existing panel potentiometer supplier discontinued production of a part used on an established and popular piece of equipment. To avoid a costly redesign, an existing panel potentiometer needed to be adapted to meet the customer’s electrical requirements. It would also have to fit the control panel insertion / retention envelope and existing markings, in addition to the PCB assembly attachment system.
DC-Link Capacitors With Tab Terminals For Harsh Vibration Profiles
Challenge
Our customer was evaluating a solution for power electronics equipment that required the use of several DC-Link capacitors on the same PCB, while ensuring that the devices would support critical vibration profiles. The products being considered for the application had a significantly high mass of around 100 g, and were attached to the PCB via four lead wires with 1.2 mm diameters. While testing these parts under severe vibration profiles, the customer reported broken lead wires. The challenge was clear: how can such high mass parts withstand severe vibration profiles, while maintaining a similar footprint on the PCB?
mmWave Loss and Unstable Performance in a Satellite Payload
Challenge
While developing a next‑generation Ka‑band and W‑band satellite payload for a low‑Earth‑orbit communications constellation, an RF systems engineer encountered an unexpected challenge. Although the team designed a GaN power amplifier and low‑noise receiver chain to operate above 80 GHz, system testing revealed significant performance degradation. The active devices met their specifications, but once the signal left the die, system performance collapsed: Insertion loss exceeded the link budget by 1.5 dB Parasitic inductance from wire bonds and interconnects distorted matching Board-to-board variation caused gain and phase inconsistencies across flight units Commercial passive components were too large and introduced resonances above 70 GHz The design relied on an advanced organic PCB with thick‑film passives and LTCC modules. Despite extensive tuning and redesign cycles, performance drifted from build to build, introducing unacceptable risk to schedule and qualification.
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